In Japanese Laid-open Patent Publication No. 2007-310600, there is disclosed a dual port type FIFO (first-in first-out) memory control circuit whose clocks differ on a writing side and a reading side. On the writing side, a control to write data into the FIFO memory in which a state of an available capacity of the FIFO memory is considered becomes a necessity. On the reading side, a control to read data in which reading does not overtake writing becomes a necessity.
In Japanese Laid-open Patent Publication No. 5-265701, there is disclosed a FIFO memory aiming at eliminating a necessity that an external device performing writing/reading performs an inspection of a full signal or an empty signal prior to writing/reading to thereby eliminate a waiting time occurring due to the inspection.